Advances in the design and fabrication of integrated circuits have resulted in significant decreases in the size of transistors and other components forming such integrated circuits. Accordingly, the density of transistors and other components that may be formed in a semiconductor substrate of a given size has increased dramatically. Such dramatic increases in the density of components have enabled manufacturers to fabricate high capacity memory devices in the same size substrate previously required for much lower capacity devices. Similarly, for microprocessors and other logic circuits, such increased component density has enabled manufacturers to increase functionality by including additional circuitry on the substrate.
In addition to improving functionality and performance of existing types of integrated circuits, increased component density has enabled manufacturers to develop a new type of integrated circuit called an "Embedded DRAM" in which logic circuitry and dynamic random access memory ("DRAM"), or other type of memory, are formed in the same integrated circuit. In other words, the logic circuitry may be "embedded" in the DRAM. FIG. 1 is a block diagram of an Embedded DRAM 11 including logic circuitry 13 and a DRAM 15 formed in a semiconductor substrate 17. The logic circuitry 13 may be designed to perform a specific function, or may be more general purpose circuitry, such as a microprocessor performing a variety of different tasks. The logic circuitry 13 is coupled to the DRAM 15 through an address bus 19, internal data bus 21, and control bus 23, and applies address, data, and control signals on these respective busses to transfer data to and from the DRAM 15. The logic circuitry 13 is further coupled to external terminals 25 on which the logic circuitry transfers information to and from external circuits (not shown in FIG. 1) coupled to the Embedded DRAM 11.
In the Embedded DRAM 11, forming the logic circuitry 13 and the DRAM 15 in the same semiconductor substrate 17 yields numerous performance benefits. First, the bandwidth of the DRAM 15 may be substantially increased by increasing the width N of the internal data bus 21, where N may be 128, 256, or 512 bits, or even wider. As understood by one skilled in the art, increasing the width N of the internal data bus 21 increases the bandwidth of the DRAM 15 by enabling more data to be transferred during each access of the DRAM 15. In a conventional DRAM, an external data bus of the DRAM has a width that is limited by a number of factors, including the number of pins that can physically be formed on a package containing the DRAM and noise generated by switching multiple data lines in parallel, as understood by one skilled in the art. In contrast, the internal data bus 21 of the Embedded DRAM 11 requires no external pins, but is instead directly connected to the logic circuitry 13 through traces formed on the substrate 17. Thus, the width N may be very wide which, in turn, dramatically increases the bandwidth of the DRAM 15.
Additional advantages of the Embedded DRAM 11 over conventional discreet interconnected devices include lower power consumption and lower electromagnetic radiation due to the shorter lengths of conductive traces comprising the internal data bus 21. Furthermore, transmission line effects such as propagation delays are likewise alleviated due to such reduced lengths of the internal data bus 21. The shorter line lengths and corresponding reduced capacitance of individual lines in the bus 21 also reduce the noise resulting when switching the N lines in parallel.
In one application of the Embedded DRAM 11, the logic circuitry 13 is a microprocessor and the DRAM 15 is directly coupled to the microprocessor via the internal data bus 21. As understood by one skilled in the art, a memory controller is typically required between a conventional DRAM and a microprocessor because the DRAM has a much lower bandwidth than the processor. Thus, a conventional DRAM creates a "bandwidth bottleneck" that limits the speed at which a computer system including the DRAM and the processor can execute a program. In contrast, in the Embedded DRAM 11 the internal data bus 21 provides a very high bandwidth between the processor 13 and DRAM 15, making the Embedded DRAM 11 well suited to applications requiring very high bandwidths, such as networking, multimedia, and high-resolution graphics systems.
During the manufacture of the Embedded DRAM 11, the DRAM 15 needs to be tested just as with conventional DRAMs. Testing the DRAM 15, however, presents new problems not encountered when testing conventional DRAMs. More specifically, an external memory tester (not shown in FIG. 1) must transfer test data to and from the memory cells in the DRAM 15. The memory tester must be coupled to the DRAM 15 through the external terminals 25 on the Embedded DRAM 11, and must apply address, control, and data signals on such external terminals to transfer data to and from the memory cells in the DRAM 15. Due to the wide internal data bus 21 of the DRAM 15, however, there are many fewer external terminals 25 available on the Embedded DRAM 11 than there are data lines in the internal data bus 21. For example, if the internal data bus 21 is 512 bits wide, the Embedded DRAM 11 cannot include 512 external data terminals plus address and control terminals due to the physical limitations of forming such external terminals 25. Thus, in an Embedded DRAM there is a problem in transferring data between the DRAM and the memory tester in order to test the DRAM.
There is a need for a test circuit in an Embedded DRAM that enables a memory tester to test the DRAM portion of the Embedded DRAM.